1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device capable of supporting both a Single Bank Refresh (SBREF) operation scheme and an Advanced Refresh (AR) operation scheme.
2. Description of the Related Art
A single bank refresh (SBREF) operation scheme is an operation scheme where a refresh operation may be performed independently in each bank of a semiconductor memory device having a plurality of banks. In other words, the semiconductor memory device supporting the single bank refresh (SBREF) operation scheme may enable the plurality of banks to receive different commands and operate at an interval of Ras to Ras delay tRRD. For example, in a semiconductor memory device having a first bank and a second bank, although the first bank is in the middle of performing a refresh operation in response to a refresh command, the second bank may perform a normal data input/output operation in response to a normal read/write command after the interval of the delay tRRD passes. Similarly, although the first bank is in the middle of performing a normal data input/output operation in response to a normal read/write command, the second bank may perform a refresh operation in response to a refresh command after the interval of the delay tRRD passes. While all the multiple banks perform a refresh operation at the interval of the delay tRRD, all the banks are not to perform a normal read/write operation.
Since each of the multiple banks independently performs a refresh operation in the single bank refresh (SBREF) operation scheme, the refresh cycle tRFC at which a refresh operation is performed in each bank becomes an active pre-charge time tRP which should be ensured at least. In other words, the length of time ensured for each refresh operation is shortened due to the single bank refresh (SBREF) operation.
For this reason, the semiconductor memory device that supports the single bank refresh (SBREF) operation scheme may not perform a series-type advanced refresh (AR) operation where a plurality of word lines are enabled at an interval of time within the refresh cycle tRFC of the refresh operation performed in each bank. Instead, it performs a parallel-type advanced refresh (AR) operation in which the multiple word lines are simultaneously enabled within the refresh cycle tRFC. Here, the advanced refresh (AR) operation means an operation where multiple word lines are enabled during one refresh cycle.
When the absolute time of the Ras to Ras delay tRRD (which is a standard for a minimum operation time interval between the banks) is compared with the absolute time of the active pre-charge time tRP (which is a standard minimum time ensured for the refresh cycle tRFC) of each bank in the semiconductor memory device supporting the single bank refresh (SBREF) operation scheme, the Ras to Ras delay tRRD is generally smaller than the active pre-charge time tRP. Accordingly, when the parallel-type advanced refresh (AR) operation is performed in the semiconductor memory device supporting the single bank refresh (SBREF) operation scheme, the following concerns arise.
FIG. 1 is a timing diagram illustrating the concerns that arise when a parallel-type advanced refresh (AR) operation is performed in a the semiconductor memory device supporting the single bank refresh (SBREF) operation scheme in accordance with a prior art.
Referring to FIG. 1, when there are two banks and the parallel advanced refresh (AR) operation is performed in the semiconductor memory device supporting a single bank refresh (SBREF) operation scheme, it is an example of where a single bank refresh command BK<0> SBREF is applied to a first bank BK<0> and a refresh operation is performed, and then an active command BK<1> ACT is applied to a second bank BK<1> at an interval of Ras to Ras delay tRRD and a normal active operation is performed.
To be specific, the single bank refresh command BK<0> SBREF is applied to the first bank BK<0> and the refresh operation is performed in a section where an advanced enable signal AR_REF EN is enabled. The single bank refresh command BK<0> SBREF may be maintained during an interval of a refresh cycle tRFC. Also, while the refresh operation is performed in the first bank BK<0> during the advanced refresh (AR) operation, the internal addresses BAX12<0> and BAX12<1> are all enabled in response to the disabling of an input address ADD<12>.
One of characteristics of an address decoding method for the advanced refresh (AR) operation is that the internal addresses BAX12<0> and BAX12<1> have two values even though the input address ADD<12> has one value. When the refresh operation is performed in the section where the advanced enable signal AR_REF EN is enabled, two values of the internal addresses BAX12<0> and BAX12<1> are controlled in response to one input address ADD<12> in order to simultaneously enable two word lines in one bank. For example, in the section where the advanced enable signal AR_REF EN is enabled, the internal addresses BAX12<0> and BAX12<1> are disabled to a logic ‘low’ level when the input address ADD<12> is enabled to a logic ‘high’ level, and the internal addresses BAX12<0> and BAX12<1> are enabled to a logic ‘high’ level when the input address ADD<12> is disabled to a logic ‘low’ level. To simplify the description, just one input address ADD<12> among many input addresses (not shown) is illustrated in the drawing. During actual operation of the semiconductor memory device, the multiple word lines included in one bank are selected in pairs corresponding to each of all input addresses (not shown).
As described above, when the refresh operation is performed in the first bank BK<0>, the internal addresses BAX12<0> and BAX12<1> are simultaneously enabled and the advanced refresh (AR) operation is performed. Then, two word lines included in the first bank BK<0> among the multiple word lines are simultaneously enabled. The enabled internal addresses BAX12<0> and BAX12<1> are kept in the enabling state during the interval of the refresh cycle tRFC where the single bank refresh command BK<0> SBREF is enabled.
After the single bank refresh command BK<0> SBREF is applied to the first bank BK<0>, the active command BK<1> ACT is applied to the second bank BK<1> at the interval of the Ras to Ras delay tRRD and the normal active operation is performed. The active command BK<1> ACT is maintained during an active pre-charge time tRP.
When the active command BK<1> ACT is inputted, the advanced refresh (AR) operation may not be performed. Thus, one word line is to be enabled in one bank. Whether or not the two internal addresses BAX12<0> and BAX12<1> are enabled is determined in response to whether or not the input address ADD<12> is enabled. For example, when the input address ADD<12> is enabled to a logic ‘high’ level while the active command BK<1> ACT is enabled, the first internal address BAX12<0> between the two internal addresses BAX12<0> and BAX12<1> is disabled to a logic ‘low’ level and the second internal address BAX12<1> between the two internal addresses BAX12<0> and BAX12<1> is enabled to a logic ‘high’ level. On the contrary, when the input address ADD<12> is disabled to a logic ‘low’ level while the active command BK<1> ACT is enabled, the first internal address BAX12<0> between the internal addresses BAX12<0> and BAX12<1> is enabled to a logic ‘high’ level and the second internal address BAX12<1> between the internal addresses BAX12<0> and BAX12<1> is disabled to a logic ‘low’ level.
As shown in the drawing, before the active command BK<1> ACT is applied to the second bank BK<1> and the normal active operation is performed, the single bank refresh command BK<0> SBREF is applied to the first bank BK<0> and the refresh operation is performed. Thus, there is a concern that the internal addresses BAX12<0> and BAX12<1> are all enabled to a logic ‘high’ level in the early section of the normal active operation of the second bank BK<1>. In other words, the two word lines are to be simultaneously enabled in response to the internal addresses BAX12<0> and BAX12<1> in the first bank BK<0>, and just one word line is to be enabled in response to one address that is enabled between the Internal addresses BAX12<0> and BAX12<1> in the second bank BK<1>. However, in actuality, the two word lines are simultaneously enabled in the second bank BK<1>. When the two word lines are simultaneously enabled in the section where the active command BK<1> ACT is applied to the second bank BK<1>, a collision occurs between the data inputted and outputted during a normal active operation to/from the inside of the second bank BK<1>, and as a result, the normal active operation may not be performed.
The above-described concern does not arise when a general refresh operation where just one word line is refreshed is performed in the semiconductor memory device supporting the single bank refresh (SBREF) operation scheme, instead of the advanced refresh (AR) operation in which many word lines are enabled during one refresh operation.
In addition, the above-described concern does not arise when the single refresh operation is sequentially performed at the interval of the Ras to Ras delay tRRD, when the normal active operation is sequentially performed at the interval of the Ras to Ras delay tRRD, or when the single refresh operation is sequentially performed at the Interval of the Ras to Ras delay tRRD subsequent to the normal active operation in the two different banks, although the parallel-type advanced refresh (AR) operation is performed in the semiconductor memory device supporting the single bank refresh (SBREF) operation scheme.
The above-described concern does not arise when each of the two different banks receives a different address signal through an Independent address line in the semiconductor memory device supporting the single bank refresh (SBREF) operation scheme. However, considering there are a large number of banks included in the semiconductor memory device, it is not desirable to independently dispose the address line for each bank since the area occupied by the address line is increased.
As the semiconductor memory device operates faster and faster, the single bank refresh (SBREF) operation and the advanced refresh (AR) operation become more and more necessary. Therefore, the above-described concerns may be a significant issue affecting a normal operation of a semiconductor memory device.